1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device with a fuse box and a method for fabricating the same.
2. Description of Related Art
The more the manufacturing technology of semiconductor devices improves, the more a chip size of the semiconductor devices is reduced to incorporate as many chips as possible in a wafer.
Generally, the semiconductor device includes a bonding pad region, in which bonding pads are formed, and a fuse region, in which a fuse box, through which a fuse cutting process is performed, is formed. The bonding pad region and the fuse region have not been reduced in size in comparison to the chip size reduction.
FIGS. 1A to 1D illustrate a conventional method of forming a fuse box and a bonding pad in a fuse region and a bonding pad region, respectively.
Referring to FIG. 1A, a semiconductor substrate 100 has a fuse region 101 and a bonding pad region 102. A plurality of polysilicon fuses 110 are then formed in the fuse region 101. When a polysilicon layer is patterned in a memory cell region (not shown) to form a bit line, the fuses 110 may be formed concurrently in the fuse region 101.
A first interlayer insulating film 120 is formed on the semiconductor substrate 100 including the fuses 110, and an etching stop layer 130 comprised of polysilicon is sequentially formed on the first interlayer insulating film 120. The etching stop layer 130 may be formed simultaneously when a polysilicon layer for a capacitor plate is formed in the memory cell region.
Next, a second interlayer insulating film 140 is formed on the etch stop layer 130 and a first metal line 150 is sequentially formed in the bonding pad region 102 on the second interlayer insulating film 140.
Referring to FIG. 1B, a third interlayer insulating film 160 is formed over the metal line 150. Subsequently, the third interlayer insulating film 160 in the bonding pad region 102 is etched to form an opening 161 therein to expose a portion of the first metal line 150. Simultaneously, the third interlayer insulating film 160 and the second interlayer insulating film 140 in the fuse region 101 are etched to form a via hole 165 therein to expose a portion of the etching stop layer 130.
Next, a metal layer is deposited on the semiconductor substrate 100 and patterned to form a second metal line 170 in the bonding pad region 102. Also, a guard ring 175 is formed in the fuse region 101 in the via hole 165. The second metal line 170 is connected to the first metal line 150 via the opening 161.
Turning to FIG. 1C, a passivation layer 180 is formed on the semiconductor substrate 100.
Referring to FIG. 1D, the passivation layer 180 is etched to expose the second metal line 170, thereby forming a bonding pad opening 190 in the bonding pad region 102.
In addition, the passivation layer 180, the second and the third interlayer insulating films 140 and 160, and the etch stop layer 130 are sequentially etched to expose the first interlayer insulating film 120 over the fuses 110, thereby forming the fuse box 195 in the fuse region 101.
In the conventional semiconductor device described above, the bonding pad region and the fuse region are separately arranged in a peripheral region of the semiconductor substrate, which is an obstacle to reduction of the chip size.